This invention relates to pulse-width modulation systems. More specifically, this invention relates to linear pulse width modulation systems that provide a pulse-width modulated (PWM) signal that has a duty cycle from 0-100% that varies linearly with a control voltage signal.
A pulse-width modulator is a circuit that generates a PWM signal from a DC control voltage and a periodic analog waveform such as a triangular waveform. A previously known pulse width modulator 10 is shown in FIG. 1. Pulse-width modulator 10 comprises comparator 14 that compares a control voltage VC at its non-inverting input to periodic analog waveform signal VW generated by waveform generator 12 at its inverting input to generate PWM signal VPWM. The comparator provides VPWM that alternates between LOW (e.g., 0 volts) and HIGH (e.g., 5 volts) in response to the voltage difference between the inverting and non-inverting inputs.
A PWM signal is a periodic signal that has an amplitude that alternates between LOW and HIGH, and has a duty cycle of between 0-100%. The period of VPWM is set by the period of VW. The duty cycle of VPWM is typically defined as the percentage of time that VPWM is HIGH during its period. The duty cycle of VPWM is set by the value of VC, and varies based on changes in VC.
Many applications require pulse-width modulators that provide a PWM signal having a duty cycle that varies linearly with the control voltage over the entire range of duty cycles from 0% to 100%. The duty cycle of the PWM signal may vary non-linearly with VC when the output signal of the comparator in the pulse-width modulator has varying propagation delays. The propagation delay of comparator 14 is the time required for its output signal (VPWM) to reach the midpoint between the LOW and HIGH values from the time when the voltage difference between the non-inverting and inverting inputs passes through zero. There are two distinct propagation delays: tPLH is the propagation delay when VPWM transitions from LOW to HIGH, and tPHL is the propagation delay when VPWM transitions from HIGH to LOW.
Example of signals VW, VC, and VPWM for circuit 10 are shown in FIG. 2. VW varies between VMAX and VMIN, and VPWM has two states (HIGH and LOW). Ideally, VPWM is HIGH when VC greater than VW, and VPWM is LOW when VC less than VW. In reality, however, comparator 14 has non-zero propagation delays tPHL 20 and tPLH 22. In particular, tPHL 20 is the difference between the time when VW crosses from just below to just above VC and the time when VPWM reaches the midpoint between HIGH and LOW, and tPLH 22 is the difference between the time when VW crosses from just above to just below VC and the time when VPWM reaches the midpoint between LOW and HIGH.
Propagation delays tPHL and tPLH may vary as VC varies between VMAX and VMIN due to variations in the overdrive (i.e., the magnitude of the difference between the voltages at the non-inverting and inverting inputs of the comparator), and the finite slew rate of the comparator""s internal nodes. For example, tPLH increases and tPHL decreases as VC approaches VMIN, and tPLH decreases and tPHL increases as VC approaches VMAX.
FIG. 3 is a graph of the duty cycle of signal VPWM of circuit 10 where VW is a symmetrical triangular periodic waveform signal. The peak-to-peak amplitude of VW is its maximum voltage VMAX minus its minimum voltage VMIN. Control voltage VC varies between VMAX and VMIN causing the duty cycle of VPWM to vary between 100% and 0%. Variations in propagation delays tPHL and tPLH of comparator 14 cause non-linearity 38 in VPWM near 100% duty cycle when VC is near VMAX (e.g. when VC is greater than 80% of the peak-to-peak amplitude of VW), and non-linearity 39 in VPWM near 0% duty cycle when VC is near VMIN (e.g. when VC is less than 20% of the peak-to-peak amplitude of VW). Non-linearities in VPWM near 100% and 0% duty cycles also exist in pulse-width modulators that use asymmetrical sawtooth periodic waveforms.
A high speed comparator may be used to achieve a more linear relationship between VC and the duty cycle of VPWM. The duty cycle of the PWM signal output of a high speed comparator used in a pulse-width modulator is able to approach closer to 0% and 100% before propagation delay variations cause non-linearities in the relationship between VC and VPWM. High speed comparators, however, typically require significantly more power and more complex circuitry than a standard comparator.
It would, however, be desirable to provide a pulse width modulator that has substantially constant propagation delays over a full range of duty cycles without significantly added power consumption and complex circuitry.
It is therefore an object of the invention to provide a pulse width modulator that has substantially constant propagation delays over a full range of duty cycles without significantly added power consumption and complex circuitry.
These and other objects of the present invention are provided by a pulse width modulator that includes a plurality of comparators, a multiplexer, and at least one waveform generator that generates a plurality of periodic waveform signals. Each of the plurality of comparators monitors control voltage VC and compares it to one of the periodic waveform signals. Each of the periodic waveform signals is time delayed with respect to the other waveform signals.
The outputs of the comparators are coupled to inputs of the multiplexer. The multiplexer selects the output signal of one of the comparators to be the PWM signal when the periodic waveform signal input to that comparator is not near its maximum or minimum voltage. During this time interval, transitions in the output signal of the selected comparator have substantially constant propagation delays.
Because each periodic waveform is time delayed with respect to the other periodic waveforms, the output of only one comparator is selected as the PWM signal during each cycle of the PWM signal. By using multiple comparators and periodic waveforms, the multiplexer is able to xe2x80x9cstitch togetherxe2x80x9d a composite PWM signal that uses the output signal of each comparator only when that comparator has substantially constant propagation delays. Low speed, low power comparators may be used in the present invention to achieve a PWM signal with a duty cycle that varies linearly with the control voltage over a full range of duty cycles. The present invention also provides methods for generating a PWM signal with a duty cycle that varies linearly with the control voltage over a full range of duty cycles.